1. Field of the Invention
This invention relates to computing systems, and more particularly, to simulating execution of instructions in a simulation environment.
2. Description of the Relevant Art
Modeling the behavior of a circuit or chip with a simulation tool is often helpful in product development. Consequently, simulation tools are in widespread use in industry and research communities. Generally speaking, simulation tools are used to validate digital logic and other designs prior to fabrication of the design. In many cases, the simulation tool may include both a functional mode and a timing mode. In addition, the simulation tool may provide a graphical user interface (GUI) for the user to interact with the simulation controls and the simulation results. Alternatively, a user may use text commands to interact with the tool and even use scripts to automatically send batch jobs to a server simulation environment.
In some cases, the simulation tool (or “simulator”) may be used to estimate the effect on performance of new design techniques. Some of these techniques include adding new instructions or modifying existing instructions to take advantage of potential hardware design practices. One such technique is augmenting the instruction set architecture (ISA) to include wider and enhanced vector instructions. The performance of multimedia, scientific and financial applications depend on support for vector instructions such as single-instruction-multiple-data (SIMD) instructions. The hardware design modifications to support these wider vector instructions may include widening the SIMD register file, increasing the number of SIMD lanes in a datapath, modifying control logic to increase the number of supported operands in an instruction, and modifying the memory bus architecture as just some potential examples.
The modifications of the hardware offering on-chip enhancements may not be completed until simulations have provided results indicating which modifications provide the desired performance or characteristics. While simulators may be used to analyze various hardware modifications, compilers are typically not enhanced to support such modifications until the hardware design is available. Unfortunately, not having such a compiler available can make developing and validating new hardware digital logic design with a simulator more difficult. One solution is to add new instructions to the ISA without having simulations to accurately estimate the effects of including such instructions. Disadvantages of this approach include unforeseen side effects, such as memory or other bottlenecks being added to the design, which may necessitate expensive post-silicon redesign. For example, wider vector instructions may encounter bandwidth bottlenecks which were not encountered by previous vector instructions. Additionally, a new feature such as support for scatter/gather memory accesses may result in unforeseen long latencies due to the added complexity.
In view of the above, efficient methods and systems for simulating new instructions without compiler support for the new instructions are desired.